How Gen AI will redefine the chip design process

In our first article, we build on ways Gen AI will revolutionize the semiconductor chip design and manufacturing process, as outlined in the first article of this series (Part 1 – How Gen AI will revolutionize the semiconductor industry). Here we explore the current applications (Now Technology) as well as forthcoming possibilities (Near Technology)

Gen AI encompasses a diverse array of applications throughout the silicon design and manufacturing flows, ranging from ML-driven architecture exploration to automated RTL coding, test suite generation, floorplan optimization, bug tracking, and predictive modeling for manufacturing processes. These applications aim to shorten design cycles, increase productivity, reduce costs, and improve overall product quality, aligning with the industry’s goal of continuous improvement.

While Electronic Design Automation (EDA) companies have made strides in AI integration, Gen AI propels further advancements by addressing holistic data interdependencies across design and manufacturing workflows, while emphasizing IP protection and data security. Indeed, the data generated throughout the design phase is a gold mine that every silicon company would want to keep tightly protected. Unlike traditional tool-centric approaches, Gen AI focuses on comprehensive solutions that recognize the intricate relationship of data across all design stages and unlock new opportunities for innovation and efficiency.

The integration of artificial intelligence into semiconductor design processes through Gen AI empowers continuous improvement to optimize efficiency, enhance product quality, and transform competitiveness in the industry. By fostering collaboration between AI specialists and semiconductor SMEs, companies can unlock the full potential of Gen AI, to drive innovation and shape the future of silicon design.

Innovating the chip design with the AI revolution (Now Technology)

The semiconductor chip design process is complex, and it involves various stages, from system specifications, architectural design, functional design, logic design, circuit design, and physical design verification prior to manufacturing. The chip development design process requires a delicate balance of Performance, Power, Area (PPA), while also adhering to stringent design rules. This means semiconductor companies must follow an iterative process to optimize designs.

The adoption of Gen AI into chip design processes yields numerous benefits, including competitive differentiation, innovation opportunities, and the creation of valuable IP assets through collaborative ventures.

When we look at today’s technology (Now technology), ready solutions are available to streamline this complex process and improve productivity. These tools pre-empt bugs ahead of time with root cause analysis to significantly reduce iterations. Thus, the utilization of costly compute farm resources, plus minimizing design errors, leads to improvements in overall chip design quality. Some of the commonly available solutions are:

1. Synopsys DSO.ai™ (Design Space Optimization AI), searches for optimization targets in large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area (PPA).
2. Cadence Verisium™ offers AI-enhanced verification, debugging, and testing capabilities. The platform optimizes verification workloads, boosts coverage, and accelerates root-cause analysis of bugs.
3. In early 2023, Synopsys™ launched a full-stack AI-driven EDA (Electronic Design Automation) suite that employs AI across architecture, design, and manufacturing stages to automate many tedious and repetitive tasks, thus liberating engineers time for enhancing chip quality.

Thanks to AI, these tools can enhance the semiconductor chip design process by assisting chip designers in creating, verifying, and optimizing designs faster and with better quality. This shift was transformative for the semiconductor industry, overcoming challenges of ever-increasing complexity and design cost.

Innovating the chip design with generative AI revolution (Near Technology)

Semiconductor chip designs are becoming increasingly complex in the face of ever-emerging compute-intensive applications propelling the need for advanced node chips. Chip design complexities also continued to increase over the last few years, posing significant challenges for engineers. This process requires incredible attention to detail as a single mistake can be costly. This is where generative AI can play a transformative role.

Generative AI encompasses the collecting and preprocessing of data from prior designs, the training of machine learning models, and their seamless integration into design flows for optimization. This shift necessitates designers to adopt new workflows with a data-driven approach. This transformative approach is showcased through the introduction of GenAI-powered design Co-Pilots by several companies. These Co-Pilots streamline processes, leveraging existing design data including requirements, specifications, IP details, and bug histories, to offer personalized guidance to designers and engineers. They excel in scenario exploration, rapidly evaluating design alternatives, and mitigating risks. Through continuous learning from historical data and user feedback, these Co-Pilots evolve into tailored tools, accelerating the design process while enhancing product quality. These tools don’t just facilitate collaboration among design teams but also serve as repositories of collective intelligence.

For instance, Synopsys’s AI tool, called Synopsis.ai CoPilot announced last fall, is intended to answer questions about how to use the company’s design tools and can create workflow scripts. It can also generate RTL, a form of chip design language that specifies chip architecture, just by conversing in plain English.

Now, let us take this idea to the next level.

Imagine having a tool that can learn from numerous existing designs of recent years.  A tool to learn about chip characteristics like performance, power, transistor size, process technology, and materials used, and a tool to use this data to prepare and recommend new models of chip design for industry-specific use-cases like Ultra-low-power, IoT (Internet of Things), and Compute.

Today, a compelling instance highlighting the significant advancements facilitated by a high degree of automation in chip development is proprietary design generator tools. These tools enhance the efficiency, quality, and time-to-market outcomes. Engineers utilize these design generator tools to delineate the parameters of the System-on-a-Chip (SoC) through a specifications framework based on standard applications like Excel. The tool then processes this specification, orchestrating the integration of semiconductor Intellectual Properties (IP) according to the outlined criteria to construct the SoC. The design generator tools assist beyond integration, conducting comprehensive quality assessments and generating essential collateral for subsequent phases of development. These design tools also significantly impact the streamlining of the efforts required for SoC Register Transfer Level (RTL) design.

With the industry’s progression towards Generative Artificial Intelligence (Gen-AI), a pressing need arises for our existing tools to evolve, to incorporate a blend of automation, AI, and Gen AI capabilities, seamlessly. We believe it is not far when design generator tools will leverage Gen-AI features to augment their automation prowess further. As an expected use case, it could expand its capabilities to generate output code in various programming languages and align collateral generation with diverse formatting requirements for subsequent development stages. Better yet, we could use GenAI to build better chips to run GenAI.

Additionally, as the adoption of chiplets grows, generative AI can help make design and verification processes more effective. The biggest thing that separates chiplets from the SoC is the partition and interconnect. Imagine having a generative AI-based design tool that can help improve productivity when partitioning the chiplets. The tool will do this by learning from various Chiplet designs about Performance, Power, Area, Memory, and I/O characteristics to help optimize the silicon block, this allows designers to meet PPA target specs and cost challenges of a design. It does leave us wondering though, how might minor changes in the design affect a chiplet’s overall performance and characteristics? And can it be predicted based on previous designs?

Generative AI offers immense potential to revolutionize the analog and digital chip design process, starting by tackling executive repetitive tasks efficiently and offering predictive capabilities to designers on future designs. But this journey will be an experience with a lot of learning.

In the next series of articles, we will cover ways generative AI can simulate future demand to adjust the manufacturing process to plan, in advance, the indicators that will drive changes. We call it the Simulated Future.

So, we will conclude this article with three questions for our readers:

1. When will generative AI be integral and essential to the chip design process?
2. What Challenges can we see in our current design methodologies that could be averse to the adoption of generative AI?
3. And how do we plan to get there?